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    TECHNIQUES FOR DIE TILING
    2.
    发明申请
    TECHNIQUES FOR DIE TILING 有权

    公开(公告)号：US20220115367A1

    公开(公告)日：2022-04-14

    申请号：US17556660

    申请日：2021-12-20

    Applicant: Intel Corporation

    Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI

    IPC: H01L25/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/29 ,  H01L21/683 ,  H01L23/31

    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

    CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
    3.
    发明申请
    CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS 有权

    公开(公告)号：US20220238458A1

    公开(公告)日：2022-07-28

    申请号：US17716947

    申请日：2022-04-08

    Applicant: Intel Corporation

    Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

    IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

    CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
    4.
    发明申请
    CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS 审中-公开

    公开(公告)号：US20200258847A1

    公开(公告)日：2020-08-13

    申请号：US16274086

    申请日：2019-02-12

    Applicant: Intel Corporation

    Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
    5.
    发明申请
    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING 有权

    公开(公告)号：US20230130944A1

    公开(公告)日：2023-04-27

    申请号：US18089213

    申请日：2022-12-27

    Applicant: Intel Corporation

    Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

    IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

    CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
    6.
    发明申请
    CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS 有权

    公开(公告)号：US20220115334A1

    公开(公告)日：2022-04-14

    申请号：US17556667

    申请日：2021-12-20

    Applicant: Intel Corporation

    Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

    IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
    7.
    发明申请
    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING 有权

    公开(公告)号：US20240421073A1

    公开(公告)日：2024-12-19

    申请号：US18818285

    申请日：2024-08-28

    Applicant: Intel Corporation

    Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

    IPC: H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
    9.
    发明申请
    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING 有权

    公开(公告)号：US20230040850A1

    公开(公告)日：2023-02-09

    申请号：US17972340

    申请日：2022-10-24

    Applicant: Intel Corporation

    Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

    IPC: H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

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