Invention Application
- Patent Title: BURST-TOLERANT DECISION FEEDBACK EQUALIZATION
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Application No.: US17516502Application Date: 2021-11-01
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Publication No.: US20220123969A1Publication Date: 2022-04-21
- Inventor: Thomas J. Giovannini , Abhijit Abhyankar
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H04L25/03
- IPC: H04L25/03 ; G06F3/05 ; G06F3/06 ; G11C19/00

Abstract:
A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.
Public/Granted literature
- US11949539B2 Burst-tolerant decision feedback equalization Public/Granted day:2024-04-02
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