公开(公告)号：US10320591B2

公开(公告)日：2019-06-11

申请号：US15570703

申请日：2016-07-22

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: G06F3/06 ,  H04L25/03 ,  G11C19/00

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US10223299B2

公开(公告)日：2019-03-05

申请号：US15101870

申请日：2014-12-18

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of mother-board through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US20240193108A1

公开(公告)日：2024-06-13

申请号：US18545189

申请日：2023-12-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/00 ,  G06F13/4243

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US20220222189A1

公开(公告)日：2022-07-14

申请号：US17649773

申请日：2022-02-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US20220123969A1

公开(公告)日：2022-04-21

申请号：US17516502

申请日：2021-11-01

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US11243897B2

公开(公告)日：2022-02-08

申请号：US16862916

申请日：2020-04-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US20180294999A1

公开(公告)日：2018-10-11

申请号：US15570703

申请日：2016-07-22

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/06 ,  G11C19/00

CPC classification number: H04L25/03057 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US20240283677A1

公开(公告)日：2024-08-22

申请号：US18590039

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

CPC classification number: H04L25/03057 ,  G06F3/05 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US11949539B2

公开(公告)日：2024-04-02

申请号：US17516502

申请日：2021-11-01

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

CPC classification number: H04L25/03057 ,  G06F3/05 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US11899597B2

公开(公告)日：2024-02-13

申请号：US17649773

申请日：2022-02-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/00 ,  G06F13/4243

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.