Invention Application
- Patent Title: WIRING LAYOUT DESIGN METHOD, PROGRAM, AND RECORDING MEDIUM
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Application No.: US17438551Application Date: 2020-03-09
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Publication No.: US20220147682A1Publication Date: 2022-05-12
- Inventor: Yusuke KOUMURA
- Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Applicant Address: JP ATSUGI-SHI, KANAGAWA-KEN
- Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Current Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Current Assignee Address: JP ATSUGI-SHI, KANAGAWA-KEN
- Priority: JP2019-052490 20190320
- International Application: PCT/IB2020/052002 WO 20200309
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06N20/00 ; G06N3/08 ; G06N3/04

Abstract:
A novel wiring layout design method is provided. A wiring layout in which a starting terminal group and an end terminal group are electrically connected to each other is generated using layout information and a netlist. In the case where the wiring layout satisfies a design rule, a wiring resistance and a parasitic capacitance of the wiring layout are extracted. The layout information is updated using Q learning and a new wiring layout is generated. In the Q learning, a positive reward is given when the values of the wiring resistance and the parasitic capacitance decrease, and a weight of the neural network is updated in accordance with the reward. In the case where the new wiring layout satisfies the design rule, a wiring resistance and a parasitic capacitance of the new wiring layout are extracted. In the case where the change rate of the wiring resistance and the parasitic capacitance is high, the layout information is updated using the Q learning.
Public/Granted literature
- US12118286B2 Wiring layout design method, program, and recording medium Public/Granted day:2024-10-15
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