公开(公告)号：US20220252658A1

公开(公告)日：2022-08-11

申请号：US17611987

申请日：2020-05-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiko INOUE ,  Yusuke KOUMURA ,  Takahiro FUKUTOME

IPC: G01R31/26 ,  G01R31/28 ,  G06N3/04

Abstract: The electrical characteristics of a semiconductor element are predicted from a process list. A feature-value calculation portion and a feature prediction portion are used to predict the electrical characteristics of the semiconductor element. The feature-value calculation portion includes a first learning model and a second learning model, and the feature prediction portion includes a third learning model. The first learning model includes a step of learning the process list for generating the semiconductor element and a step of generating a first feature value. The second learning model includes a step of learning the electrical characteristics of the semiconductor element generated in accordance with the process list and a step of generating a second feature value. The third learning model includes a step of performing multimodal learning with use of the first feature value and the second feature value and a step of outputting a value of a variable used in a formula for the semiconductor element characteristics. The first to third learning models include neural networks different from each other.

公开(公告)号：US20220366928A1

公开(公告)日：2022-11-17

申请号：US17630090

申请日：2020-07-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Fumiya NAGASHIMA ,  Kengo AKIMOTO ,  Tatsuya OKANO ,  Yusuke KOUMURA ,  Seiko INOUE

IPC: G10L21/0272 ,  G10L25/30

Abstract: An audio device capable of inhibiting malfunction of an information terminal is provided. The audio device includes a sound sensor portion, a sound separation portion, a sound determination portion, and a processing portion. The sound sensor portion has a function of sensing sound. The sound separation portion has a function of separating the sound sensed by the sound sensor portion into a voice and sound other than a voice. The sound determination portion has a function of storing the feature quantity of the sound. The sound determination portion has a function of determining, with a machine learning model such as a neural network model, whether the feature quantity of the voice separated by the sound separation portion is the stored feature quantity. The processing portion has a function of analyzing an instruction contained in the voice and generating an instruction signal representing the content of the instruction in the case where the feature quantity of the voice is the stored feature quantity. The processing portion has a function of performing, on the sound other than a voice separated by the sound separation portion, processing for canceling the sound other than a voice. Specifically, the processing portion has a function of performing, on the sound other than a voice, processing for inverting the phase thereof.

公开(公告)号：US20220292332A1

公开(公告)日：2022-09-15

申请号：US17629499

申请日：2020-07-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yusuke KOUMURA ,  Koki INOUE ,  Ayana KIMOTSUKI ,  Fumiya NAGASHIMA

IPC: G06N3/04 ,  G06T7/50 ,  G06T1/60 ,  G06N3/063

Abstract: A system with high processing speed and low power consumption is provided. The system includes an imaging device and an arithmetic circuit. The imaging device includes an imaging portion, a first memory portion, and an arithmetic portion, and the arithmetic circuit includes a second memory portion. The imaging portion has a function of converting light reflected by an external subject into image data, and the first memory portion has a function of storing the image data and a first filter for performing first convolutional processing in a first layer of a neural network. The arithmetic portion has a function of performing the first convolutional processing using the image data and the first filter to generate first data. The second memory portion has a function of storing the first data and a plurality of filters. The arithmetic circuit has a function of generating a depth map of the image data.

公开(公告)号：US20240371306A1

公开(公告)日：2024-11-07

申请号：US18684958

申请日：2022-08-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuaki OHSHIMA ,  Tatsunori INOUE ,  Yusuke KOUMURA

IPC: G09G3/00 ,  G09G3/32 ,  G09G3/3233

Abstract: A display apparatus with reduced power consumption is provided. The display apparatus includes a display portion including a first region and a second region, a first driver circuit corresponding to the first region, a second driver circuit corresponding to the second region, a first circuit, a second circuit, a first signal generation circuit, and a second signal generation circuit. The first circuit has a function of generating a first image signal corresponding to a first image, and the second circuit has a function of generating a second image signal corresponding to a second image. The second image contains character information. The first signal generation circuit has a function of generating a clock signal with a first frame frequency, and the second signal generation circuit has a function of generating a clock signal with a second frame frequency lower than the first frame frequency. The display apparatus displays the first image on the first region with the first frame frequency when the first image signal is transmitted to the first driver circuit, and displays the second image on the second region with the second frame frequency when the second image signal is transmitted to the second driver circuit.

公开(公告)号：US20230066071A1

公开(公告)日：2023-03-02

申请号：US17894261

申请日：2022-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yusuke KOUMURA ,  Yuki OKAMOTO ,  Toshiki MIZUGUCHI ,  Tatsuya ONUKI ,  Hideki UOCHI

IPC: G09G3/20 ,  G09G3/3233

Abstract: A novel image correction system is provided. The image correction system includes an imaging device, a first arithmetic device, a display portion including a plurality of pixels, and a second arithmetic device. The imaging device obtains imaging data by capturing a first-gray-level image displayed on the display portion. The first arithmetic device calculates the luminous intensity of each of the pixels and a correction standard by using the imaging data. The first arithmetic device calculates correction data for each of the pixels by using the luminous intensity and the correction standard. The second arithmetic device corrects a video signal by using the correction data. The display portion displays an image using the corrected video signal. The first arithmetic device calculates correction data for pixels that emit red light, pixels that emit green light, and pixels that emit blue light and modifies the correction data by using color temperature data.

公开(公告)号：US20230024698A1

公开(公告)日：2023-01-26

申请号：US17783074

申请日：2020-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yusuke KOUMURA ,  Koki INOUE ,  Fumiya NAGASHIMA

IPC: G06N3/04 ,  G06N3/08 ,  G06V10/776 ,  G06V10/82

Abstract: A neural network model that can perform highly accurate processing on input data is provided. The neural network model includes first and second neutral networks, and the first neural network includes a first layer, a second layer, and a third layer. A feature map output from the first layer is input to the second layer and the second neural network, and a feature map output from the second neural network is input to the third layer. Given that the feature map output from the first layer when first data is input to the first neural network is a correct feature map and that the feature map output from the first layer when second data obtained by adding noise to the first data is input to the first neural network is a learning feature map, the second neural network is learned so that a feature map output from the second neural network matches the correct feature map when the learning feature map is input.

公开(公告)号：US20250028894A1

公开(公告)日：2025-01-23

申请号：US18904115

申请日：2024-10-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yusuke KOUMURA

IPC: G06F30/392 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00

Abstract: A novel wiring layout design method is provided. A wiring layout in which a starting terminal group and an end terminal group are electrically connected to each other is generated using layout information and a netlist. In the case where the wiring layout satisfies a design rule, a wiring resistance and a parasitic capacitance of the wiring layout are extracted. The layout information is updated using Q learning and a new wiring layout is generated. In the Q learning, a positive reward is given when the values of the wiring resistance and the parasitic capacitance decrease, and a weight of the neural network is updated in accordance with the reward. In the case where the new wiring layout satisfies the design rule, a wiring resistance and a parasitic capacitance of the new wiring layout are extracted. In the case where the change rate of the wiring resistance and the parasitic capacitance is high, the layout information is updated using the Q learning.

公开(公告)号：US20240161695A1

公开(公告)日：2024-05-16

申请号：US18282164

申请日：2022-03-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Minato ITO ,  Takanori MATSUZAKI ,  Munehiro KOZUMA ,  Yuki OKAMOTO ,  Yusuke KOUMURA

IPC: G09G3/3233 ,  H10K59/131

CPC classification number: G09G3/3233 ,  H10K59/131 ,  G09G2300/0809 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2340/0442

Abstract: A display apparatus with a novel structure is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a driver circuit region, and the second layer includes a pixel array. The pixel array includes a plurality of pixel regions. The driver circuit region includes a control circuit unit and a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to any one of the plurality of pixel regions. The local driver circuit has a function of outputting a driving signal for driving a plurality of pixels included in the corresponding pixel region. The control circuit unit has a function of comparing definition data of an input image signal and aspect ratio data of the pixel array to determine a first region where display is performed and a second region where display is not performed, and outputting, to the local driver circuit corresponding to the second region, a control signal for stopping output of the driving signal.

公开(公告)号：US20230004704A1

公开(公告)日：2023-01-05

申请号：US17846110

申请日：2022-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Minato ITO ,  Yusuke KOUMURA ,  Tatsuya ONUKI

IPC: G06F30/392

Abstract: The circuit layout generation system includes a memory portion, a limitation data arithmetic portion, and a layout data arithmetic portion. The memory portion is configured to store circuit connection data and first limitation data. The circuit connection data is data regarding connection of a transistor and a capacitor included in a pixel circuit. The first limitation data includes data that determines a wiring interval of the transistor and a wiring interval of the capacitor and data that determines placement coordinates of the transistor and the capacitor. The limitation data arithmetic portion is configured to generate second limitation data on the basis of the circuit connection data and the first limitation data and store the second limitation data in the memory portion. The second limitation data is data that determines the placement of the transistor and the capacitor designated by the placement coordinates so that the transistor and the capacitor are positioned close to each other. The layout data arithmetic portion is configured to generate layout data on the basis of the circuit connection data, the first limitation data, and the second limitation data.

公开(公告)号：US20220147682A1

公开(公告)日：2022-05-12

申请号：US17438551

申请日：2020-03-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yusuke KOUMURA

IPC: G06F30/392 ,  G06N20/00 ,  G06N3/08 ,  G06N3/04

Abstract: A novel wiring layout design method is provided. A wiring layout in which a starting terminal group and an end terminal group are electrically connected to each other is generated using layout information and a netlist. In the case where the wiring layout satisfies a design rule, a wiring resistance and a parasitic capacitance of the wiring layout are extracted. The layout information is updated using Q learning and a new wiring layout is generated. In the Q learning, a positive reward is given when the values of the wiring resistance and the parasitic capacitance decrease, and a weight of the neural network is updated in accordance with the reward. In the case where the new wiring layout satisfies the design rule, a wiring resistance and a parasitic capacitance of the new wiring layout are extracted. In the case where the change rate of the wiring resistance and the parasitic capacitance is high, the layout information is updated using the Q learning.