Invention Application
- Patent Title: IMPEDANCE CALIBRATION CIRCUIT AND METHOD OF CALIBRATING IMPEDANCE IN MEMORY DEVICE
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Application No.: US17352527Application Date: 2021-06-21
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Publication No.: US20220148630A1Publication Date: 2022-05-12
- Inventor: Anil Kavala , Tongsung Kim , Chiweon Yoon , Byunghoon Jeong
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2020-0149935 20201111
- Main IPC: G11C7/10
- IPC: G11C7/10 ; H03K19/00

Abstract:
An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.
Public/Granted literature
- US11367471B2 Impedance calibration circuit and method of calibrating impedance in memory device Public/Granted day:2022-06-21
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