公开(公告)号：US20240295989A1

公开(公告)日：2024-09-05

申请号：US18538512

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Hyunjin Kwon ,  Jungjune Park ,  Chiweon Yoon ,  Youngmin Jo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F3/0625

Abstract: A storage device includes at least one nonvolatile memory device a controller configured to control the at least one nonvolatile memory device, and an interface chip connected to the controller, wherein the interface chip includes a first interface circuit configured to communicate with the controller according to a first interface protocol, a second interface circuit configured to communicate the at least one nonvolatile memory device according to a second interface protocol, and a protocol converter configured to convert the first interface protocol to the second interface protocol or to convert the second interface protocol to the first interface protocol.

公开(公告)号：US20240282378A1

公开(公告)日：2024-08-22

申请号：US18444848

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: A memory system includes a memory device having a plurality of non-volatile memories, a buffer chip connected with each of the plurality of non-volatile memories, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip. The buffer chip includes a first loop coupled to a sampler circuit and configured to perform first monitoring on the data strobe signal and first duty correction on the data strobe signal based on the first monitoring, and a second loop coupled to a multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and second duty correction on the data strobe signal based on the second monitoring. The buffer chip is configured to store first and second duty correction information for at least one of the plurality of non-volatile memories.

公开(公告)号：US20240242743A1

公开(公告)日：2024-07-18

申请号：US18368907

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyun Park ,  Jungyu Lee ,  Yumin Kim ,  Chiweon Yoon ,  Eunchan Lee

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/04 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/14

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a voltage generator configured to output a first voltage that varies according to temperature of the memory device, a second voltage that is constant regardless of the temperature, and a first reference voltage applied to at least one line among the plurality of word lines and the plurality of bit lines, and a temperature compensation circuit configured to generate a compensation offset voltage based on the first voltage and the second voltage, and output a second reference voltage based on the first reference voltage and the compensation offset voltage.

公开(公告)号：US11869860B2

公开(公告)日：2024-01-09

申请号：US17479194

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsuk Kang ,  Daehoon Na ,  Chiweon Yoon

IPC: G11C7/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G11C5/02

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  G11C5/025 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.

公开(公告)号：US20220236917A1

公开(公告)日：2022-07-28

申请号：US17479194

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsuk Kang ,  Daehoon Na ,  Chiweon Yoon

IPC: G06F3/06 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.

公开(公告)号：US09627084B2

公开(公告)日：2017-04-18

申请号：US15085498

申请日：2016-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Myoung-Won Yoon ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

Abstract: A storage device includes a nonvolatile memory device including memory blocks and a controller configured to control the nonvolatile memory device. Each of the memory blocks includes a plurality of cell strings each including at least one selection transistor and a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. The controller controls the nonvolatile memory device to perform a read operation on some of selection transistors of a selected one of the memory blocks and to perform a program operation on the selection transistors of the selected memory block according to a result of the read operation.

公开(公告)号：US20250087264A1

公开(公告)日：2025-03-13

申请号：US18958240

申请日：2024-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US12237046B2

公开(公告)日：2025-02-25

申请号：US17951567

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22

Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

公开(公告)号：US12112071B2

公开(公告)日：2024-10-08

申请号：US18217063

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G06F3/06 ,  G06F1/06 ,  G06F13/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0613 ,  G06F3/0679 ,  G06F13/1668 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

公开(公告)号：US20240312531A1

公开(公告)日：2024-09-19

申请号：US18602709

申请日：2024-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bilal Ahmad Janjua ,  Jihyun Park ,  Chiweon Yoon ,  Jungyu Lee

IPC: G11C16/30 ,  G11C16/04

CPC classification number: G11C16/30 ,  G11C16/0483

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a control logic configured to control a memory operation with respect to the plurality of memory cells, and a voltage generator configured to output a voltage for the memory operation. The voltage generator includes a charge pump configured to generate the voltage, and a peak control circuit configured to sense a current flowing from a pad, to which an external voltage is applied, to the charge pump, and control a peak of the current to be a threshold level or less based on a result of the sensing.