Apparatuses, systems, and methods for faster memory access regions. A memory array may have a fiat bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.