公开(公告)号：US20250029957A1

公开(公告)日：2025-01-23

申请号：US18906093

申请日：2024-10-03

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Raj K. Bansal ,  Takehiro Hasegawa ,  Chang H. Siau

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H10B41/41

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

公开(公告)号：US20210265370A1

公开(公告)日：2021-08-26

申请号：US17164375

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: H01L27/11531 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  G11C16/04 ,  H01L27/06 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

公开(公告)号：US10090053B2

公开(公告)日：2018-10-02

申请号：US15954282

申请日：2018-04-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US09972391B2

公开(公告)日：2018-05-15

申请号：US14971634

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20150206587A1

公开(公告)日：2015-07-23

申请号：US14161170

申请日：2014-01-22

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: G11C16/04 ,  H01L29/66 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L27/11531 ,  G11C5/145 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0694 ,  H01L27/115 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66477 ,  H01L29/78

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

Abstract translation: 已经公开了装置和方法。 一种这样的设备包括形成在基板的顶侧上的一系列存储单元。 支撑电路形成在衬底的背面，并通过衬底中的垂直互连耦合到存储器单元串。 垂直互连可以是诸如环绕衬底晶体管和/或环绕栅极晶体管的晶体管。

公开(公告)号：US11430798B2

公开(公告)日：2022-08-30

申请号：US17164375

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: H01L29/76 ,  H01L27/11531 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  G11C16/04 ,  H01L27/06 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  G11C5/14

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

公开(公告)号：US20190341394A1

公开(公告)日：2019-11-07

申请号：US16418743

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: H01L27/11531 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11546

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

公开(公告)号：US12136607B2

公开(公告)日：2024-11-05

申请号：US17718217

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Raj K. Bansal ,  Takehiro Hasegawa ,  Chang H. Siau

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H10B41/41

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

公开(公告)号：US20230061258A1

公开(公告)日：2023-03-02

申请号：US17718217

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Raj K. Bansal ,  Takehiro Hasegawa ,  Chang H. Siau

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

公开(公告)号：US20180233200A1

公开(公告)日：2018-08-16

申请号：US15954282

申请日：2018-04-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.