Invention Application
- Patent Title: HOST-RESIDENT TRANSLATION LAYER VALIDITY CHECK TECHNIQUES
-
Application No.: US17576466Application Date: 2022-01-14
-
Publication No.: US20220206959A1Publication Date: 2022-06-30
- Inventor: David Aaron Palmer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F12/14
- IPC: G06F12/14 ; G06F12/06 ; G06F21/60
Abstract:
Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
Public/Granted literature
- US11687469B2 Host-resident translation layer validity check techniques Public/Granted day:2023-06-27
Information query
