Invention Application
- Patent Title: SYSTEMS AND METHODS FOR MITIGATING CRACK PROPAGATION IN SEMICONDUCTOR DIE MANUFACTURING
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Application No.: US17137135Application Date: 2020-12-29
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Publication No.: US20220208609A1Publication Date: 2022-06-30
- Inventor: Wei Yeeng Ng , Rajesh Balachandran , Frank Speetjens , Andrew L. Li , Sukhdeep Kaur , Sangeetha P. Komanduri
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/00

Abstract:
A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
Public/Granted literature
- US11637040B2 Systems and methods for mitigating crack propagation in semiconductor die manufacturing Public/Granted day:2023-04-25
Information query
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