公开(公告)号：US20220208609A1

公开(公告)日：2022-06-30

申请号：US17137135

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Wei Yeeng Ng ,  Rajesh Balachandran ,  Frank Speetjens ,  Andrew L. Li ,  Sukhdeep Kaur ,  Sangeetha P. Komanduri

IPC: H01L21/78 ,  H01L23/00

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

公开(公告)号：US20240081057A1

公开(公告)日：2024-03-07

申请号：US17929933

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Andrew L. Li

IPC: H01L27/11582 ,  H01L21/285 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/28518 ,  H01L27/11565

Abstract: An electronic device includes a source contact adjacent to a source stack, the source stack including one or more conductive materials, tiers of alternating conductive material and dielectric materials adjacent to the source contact, pillars extending vertically through the tiers and the source contact and at least partially into the source contact, a fill material extending vertically through the tiers to the source contact, and a metal silicide material between the fill material and an upper surface of the source contact. Related devices, systems, and methods are also disclosed.

公开(公告)号：US11637040B2

公开(公告)日：2023-04-25

申请号：US17137135

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Wei Yeeng Ng ,  Rajesh Balachandran ,  Frank Speetjens ,  Andrew L. Li ,  Sukhdeep Kaur ,  Sangeetha P. Komanduri

IPC: H01L23/28 ,  H01L21/78 ,  H01L23/00

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

公开(公告)号：US10607851B2

公开(公告)日：2020-03-31

申请号：US15686526

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Andrew L. Li ,  Prashant Raghu ,  Sanjeev Sapra ,  Rita J. Klein ,  Sanh D. Tang ,  Sourabh Dhir

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L21/66 ,  H01L21/67 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

公开(公告)号：US09960114B1

公开(公告)日：2018-05-01

申请号：US15585396

申请日：2017-05-03

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US20240074177A1

公开(公告)日：2024-02-29

申请号：US17822101

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Justin D. Shepherdson ,  Swapnil A. Lengade ,  Collin Howder ,  Dheeraj Kumar ,  Andrew L. Li

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a region with a tiered stack that includes insulative, conductive, and non-conductive structures arranged in tiers. The insulative structures vertically alternate with both the conductive and the non-conductive structures. Each of the conductive structures is vertically spaced from another of the conductive structures by at least one of the non-conductive structures and at least two of the insulative structures. A composition of the non-conductive structures differs from a composition of the insulative structures. In methods of fabrication, a precursor stack is formed to include the insulative structures vertically alternating with first and second non-conductive structures. In a region of the precursor stack, the first non-conductive structures are removed, forming voids between multi-structure tier groups. Conductive structures are formed in the voids. Electronic systems are also disclosed.

公开(公告)号：US20230260840A1

公开(公告)日：2023-08-17

申请号：US18306137

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Wei Yeeng Ng ,  Rajesh Balachandran ,  Frank Speetjens ,  Andrew L. Li ,  Sukhdeep Kaur ,  Sangeetha P. Komanduri

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/28

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

公开(公告)号：US10128183B1

公开(公告)日：2018-11-13

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US20180323142A1

公开(公告)日：2018-11-08

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.