Invention Application
- Patent Title: SEMICONDUCTOR PACKAGES WITH VERTICAL PASSIVE COMPONENTS
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Application No.: US17558592Application Date: 2021-12-22
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Publication No.: US20220208746A1Publication Date: 2022-06-30
- Inventor: Jiraphat Charoenratpratoom , Phongsak Sawasdee , Wannasat Panphrom
- Applicant: UTAC Headquarters Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: UTAC Headquarters Pte. Ltd.
- Current Assignee: UTAC Headquarters Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/495 ; H01L23/00

Abstract:
An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.
Public/Granted literature
- US12230615B2 Semiconductor packages with vertical passive components Public/Granted day:2025-02-18
Information query
IPC分类: