Invention Application
- Patent Title: Gate Resistance Reduction Through Low-Resistivity Conductive Layer
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Application No.: US17658708Application Date: 2022-04-11
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Publication No.: US20220238715A1Publication Date: 2022-07-28
- Inventor: Chung-Chiang Wu , Po-Cheng Chen , Kuo-Chan Huang , Hung-Chin Chung , Hsien-Ming Lee , Chien-Hao Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/088 ; H01L29/423 ; H01L21/8234 ; H01L29/66 ; H01L29/40 ; H01L29/49
Abstract:
A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
Public/Granted literature
- US11916146B2 Gate resistance reduction through low-resistivity conductive layer Public/Granted day:2024-02-27
Information query
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