Invention Application
- Patent Title: Semiconductor Device and Method
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Application No.: US17325859Application Date: 2021-05-20
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Publication No.: US20220278098A1Publication Date: 2022-09-01
- Inventor: Li-Fong Lin , Chung-Ting Ko , Wan Chen Hsieh , Tai-Chun Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L21/8234

Abstract:
Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.
Public/Granted literature
- US11532628B2 Semiconductor device and method Public/Granted day:2022-12-20
Information query
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