公开(公告)号：US11532628B2

公开(公告)日：2022-12-20

申请号：US17325859

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Chung-Ting Ko ,  Wan Chen Hsieh ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US12051700B2

公开(公告)日：2024-07-30

申请号：US18068367

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wan Chen Hsieh ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/7851

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US20240413157A1

公开(公告)日：2024-12-12

申请号：US18742480

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wan Chen Hsieh ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US20240113164A1

公开(公告)日：2024-04-04

申请号：US18151792

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Chia Su ,  Li-Fong Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

公开(公告)号：US20230116949A1

公开(公告)日：2023-04-20

申请号：US18068367

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wan Chen Hsieh ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US20250087528A1

公开(公告)日：2025-03-13

申请号：US18402187

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yunn-Shiuan Liu ,  Li-Fong Lin ,  Chia-Hui Lin ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming a gate stack, and etching the gate stack to form a trench penetrating through the gate stack. A dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. The second dielectric layer fills the trench. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

公开(公告)号：US20230378256A1

公开(公告)日：2023-11-23

申请号：US17818057

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wen-Kai Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/41791 ,  H01L29/7851 ,  H01L21/823481 ,  H01L29/66545

Abstract: Transistor gate isolation structures and methods of forming the same are provided. In an embodiment, a device includes: an isolation region; a first gate structure on the isolation region; a second gate structure on the isolation region; and a gate isolation structure between the first gate structure and the second gate structure in a first cross-section, an upper portion of the gate isolation structure having a first concentration of an element, a lower portion of the gate isolation structure having a second concentration of the element, the first concentration different from the second concentration, the lower portion extending continuously along a sidewall of the first gate structure, beneath the upper portion, and along a sidewall of the second gate structure.

公开(公告)号：US20220278098A1

公开(公告)日：2022-09-01

申请号：US17325859

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Chung-Ting Ko ,  Wan Chen Hsieh ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.