A dead time controller includes a phase detector, a filter circuit and an amplifying circuit. The phase detector generates a detection signal by detecting a phase difference between a first driving control signal applied to a first power transistor and a second driving control signal applied to a second power transistor, the detection signal being associated with a dead time corresponding to an overlapped deactivation interval between the first and second driving control signals. The filter circuit generates a DC voltage signal by filtering and averaging the detection signal based on a pulse-width modulation (PWM) signal. The PWM signal is generated by performing a PWM on an output voltage provided at an output node coupled to a second terminal of the inductor. The amplifying circuit generates an amplified voltage signal having a voltage level proportional to the dead time by amplifying the DC voltage signal.