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公开(公告)号：US20210194365A1
公开(公告)日：2021-06-24
申请号：US16939272
申请日：2020-07-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM
Abstract: A frequency limit circuit includes a frequency-voltage converter, a compensation voltage generator and a compensator. The frequency-voltage converter generates a conversion voltage proportional to an operation frequency of the DC-DC converter based on a pulse-frequency modulation (PFM) voltage control signal indicating the operation frequency. The compensation voltage generator generates a compensation voltage based on a difference between the conversion voltage and a frequency limit voltage. The compensator adjusts a compensation current at an output node of the DC-DC converter based on the compensation voltage to restrict the operation frequency. The operation frequency of the DC-DC converter may be restricted efficiently by adjusting the compensation current through the negative feedback operation.
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公开(公告)号：US20250021119A1
公开(公告)日：2025-01-16
申请号：US18523424
申请日：2023-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM , Minshik SEOK , Daehan YU
IPC: G05F1/56
Abstract: A power management device includes a main power management integrated circuit (PMIC) and at least one sub PMIC that communicates with the main PMIC through a dedicated pin. The main PMIC includes a first pin, enables first functions associated with a first initial operation based on a battery voltage during a stand-by period before generating first output voltages based on the battery voltage and applies a first sub enable signal to the at least one sub PMIC through the first pin based on a power-on signal after completing the first initial operation. The at least one sub PMIC includes a second pin, receives the first sub enable signal through the second pin and enables second functions associated with a second initial operation based on the battery voltage, in response to an activation of the first sub enable signal.
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公开(公告)号：US20230387889A1
公开(公告)日：2023-11-30
申请号：US18154966
申请日：2023-01-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM , Jaehyuk YANG , Yongsung CHO
Abstract: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuited configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.
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公开(公告)号：US20240210976A1
公开(公告)日：2024-06-27
申请号：US18336278
申请日：2023-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM , Seongmun Park
Abstract: A regulator circuit includes a first linear regulator circuit, configured to control a voltage on an output node based on a first reference voltage and to provide first current to the output node, and a second linear regulator circuit, connected in parallel to the first linear regulator circuit and configured to provide second current to the output node, and the second linear regulator circuit is further configured to control a magnitude of the second current based on a magnitude of the first current.
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公开(公告)号：US20200343815A1
公开(公告)日：2020-10-29
申请号：US16685253
申请日：2019-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM
Abstract: A power converter for detecting oscillation of an output voltage including a switching regulator configured to perform switching so that an inductor is alternatively connected to or isolated from an external power voltage and generate the output voltage by a current that flows through the inductor and an oscillation detector configured to detect oscillation that occurs in the output voltage and output an oscillation detection signal by determining whether the oscillation belongs to an oscillation frequency detection range to be detected by the oscillation detector may be provided.
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Patent Agency Ranking
公开(公告)号：US20230221364A1
公开(公告)日：2023-07-13
申请号：US18094860
申请日：2023-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok NAM , Yus Ko , Sangho Kim , Jaehyuk Yang
IPC: G01R31/28
CPC classification number: G01R31/2843
Abstract: A device includes a function circuit that operates based on power provided by a first positive supply voltage and a first negative supply voltage, a monitoring circuit that operates based on power provided by a second positive supply voltage and a second negative supply voltage and that generates a first monitor signal based on monitoring an operation of the function circuit, and an output circuit that generates a second monitor signal based on monitoring the first positive supply voltage, generates a third monitor signal based on monitoring the second positive supply voltage, and generates an output signal that is output through one or more output pins, based on the first monitor signal, the second monitor signal, and the third monitor signal.
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公开(公告)号：US20220286043A1
公开(公告)日：2022-09-08
申请号：US17519517
申请日：2021-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM
Abstract: A dead time controller includes a phase detector, a filter circuit and an amplifying circuit. The phase detector generates a detection signal by detecting a phase difference between a first driving control signal applied to a first power transistor and a second driving control signal applied to a second power transistor, the detection signal being associated with a dead time corresponding to an overlapped deactivation interval between the first and second driving control signals. The filter circuit generates a DC voltage signal by filtering and averaging the detection signal based on a pulse-width modulation (PWM) signal. The PWM signal is generated by performing a PWM on an output voltage provided at an output node coupled to a second terminal of the inductor. The amplifying circuit generates an amplified voltage signal having a voltage level proportional to the dead time by amplifying the DC voltage signal.
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8.发明申请公开(公告)号：US20240411333A1
公开(公告)日：2024-12-12
申请号：US18648798
申请日：2024-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM , Daehan YU
Abstract: A power management integrated circuit and a method of operating the power management integrated circuit are disclosed. The power management integrated includes an upper regulator circuit that receives a system voltage as an input and outputs a first output voltage; a lower regulator circuit having the first output voltage as an input; and a Kelvin switch circuit connected between the upper regulator circuit and the lower regulator circuit. The Kelvin switch circuit includes a plurality of switches that connect any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.
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9.发明申请公开(公告)号：US20210184683A1
公开(公告)日：2021-06-17
申请号：US17000642
申请日：2020-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM
Abstract: A clock distribution circuit including a Phase Locked Loop (PLL), a first Phase Detecting and Converting (PDC) circuit, a second PDC circuit, and a clock generating and compensating (CGC)circuit may be provided. The PLL may generate reference clock signals. The first PDC circuit may generate input phase difference voltages based on phase differences between respective pairs of two reference clock signals among the reference clock signals. The second PDC circuit may generate output phase difference voltages based on phase differences between respective pairs of two power switching signals among power switching signals received from external switching regulators. The CGC circuit may generate input clock signals provided to the plurality of external switching regulators by shifting phases of the reference clock signals, and additionally control a phase of at least one of the input clock signals based on the input phase difference voltages and the output phase difference voltages.
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公开(公告)号：US20210159793A1
公开(公告)日：2021-05-27
申请号：US17165257
申请日：2021-02-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok NAM
Abstract: A power converter for detecting oscillation of an output voltage including a switching regulator configured to perform switching so that an inductor is alternatively connected to or isolated from an external power voltage and generate the output voltage by a current that flows through the inductor and an oscillation detector configured to detect oscillation that occurs in the output voltage and output an oscillation detection signal by determining whether the oscillation belongs to an oscillation frequency detection range to be detected by the oscillation detector may be provided.
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