Invention Application
- Patent Title: POWER SUPPLY REJECTION ENHANCER
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Application No.: US17213044Application Date: 2021-03-25
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Publication No.: US20220308609A1Publication Date: 2022-09-29
- Inventor: Kuan Chuang KOAY , Hua GUAN , Jize JIANG
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Main IPC: G05F1/56
- IPC: G05F1/56 ; H03F3/16
Abstract:
In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.
Public/Granted literature
- US11687104B2 Power supply rejection enhancer Public/Granted day:2023-06-27
Information query
IPC分类:
