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公开(公告)号：US20180091044A1
公开(公告)日：2018-03-29
申请号：US15274525
申请日：2016-09-23
Applicant: QUALCOMM Incorporated
Inventor： Loai Galal Bahgat SALEM , Hua GUAN , Ngai Yeung HO
IPC: H02M3/07
Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing a voltage regulator. The voltage regulator includes a power field effect transistor (FET) comprising a gate terminal. The voltage regulator further includes a charge pump, the charge pump comprising a capacitor switchably coupled to the gate terminal. The voltage regulator further includes a current outputting amplifier switchably coupled to the capacitor.
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公开(公告)号：US20170322575A1
公开(公告)日：2017-11-09
申请号：US15256315
申请日：2016-09-02
Applicant: QUALCOMM Incorporated
Inventor： Mengmeng DU , Hua GUAN , Ngai Yeung HO , Chi Fan YUNG
IPC: G05F1/575
Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
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公开(公告)号：US20250020715A1
公开(公告)日：2025-01-16
申请号：US18420736
申请日：2024-01-23
Applicant: QUALCOMM Incorporated
Inventor： Chengyue YU , Hua GUAN , Yingjie CHEN , Fan YANG , Yufei PAN , Jize JIANG , Shamim AHMED
IPC: G01R31/28
Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.
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公开(公告)号：US20220404850A1
公开(公告)日：2022-12-22
申请号：US17350535
申请日：2021-06-17
Applicant: QUALCOMM Incorporated
Inventor： Hua GUAN , Fan YANG , Hardik PATEL
IPC: G05F1/563
Abstract: Certain aspects of the present disclosure provide a power supply system. The power supply system generally includes a first voltage regulator and a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system. The power supply system may also include a current balancer circuit configured to adjust an output current of the first voltage regulator based on determined headrooms of the first voltage regulator and the second voltage regulator.
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公开(公告)号：US20170255214A1
公开(公告)日：2017-09-07
申请号：US15250737
申请日：2016-08-29
Applicant: QUALCOMM Incorporated
Inventor： Ngai Yeung HO , Hua GUAN
Abstract: Circuit techniques control multiple regulator circuits. Regulator circuits are configured to time share voltage control circuitry. The voltage control circuitry may include multiple sets of switches to selectively couple a voltage control circuit with a selected voltage regulation loop of one of the regulators.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230417828A1
公开(公告)日：2023-12-28
申请号：US17808357
申请日：2022-06-23
Applicant: QUALCOMM Incorporated
Inventor： Chengyue YU , Hua GUAN , Yingjie CHEN , Fan YANG , Yufei PAN , Jize JIANG , Shamim AHMED
IPC: G01R31/28
CPC classification number: G01R31/2896 , G01R31/2853 , G01R31/2891
Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.
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公开(公告)号：US20230198394A1
公开(公告)日：2023-06-22
申请号：US17554991
申请日：2021-12-17
Applicant: QUALCOMM Incorporated
Inventor： Jize JIANG , Hua GUAN
Abstract: A power supply circuit and techniques for voltage regulation are described. Certain aspects provide a method of supplying power by a power supply circuit. The method generally includes: generating an output voltage based on a voltage at a Vin node via a first transistor having a gate coupled to a gate of a second transistor, wherein a source of the second transistor is coupled to the Vin node and wherein a drain of the second transistor is coupled a drain of a third transistor; and sourcing a current to the third transistor, wherein during a light load condition of the power supply circuit, the current varies based on the voltage at a Vout node of the power supply circuit, and during a heavy load condition of the power supply circuit, the current is limited based on a current threshold.
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公开(公告)号：US20180136680A1
公开(公告)日：2018-05-17
申请号：US15854597
申请日：2017-12-26
Applicant: QUALCOMM Incorporated
Inventor： Mengmeng DU , Hua GUAN , Ngai Yeung HO , Chi Fan YUNG
Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
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公开(公告)号：US20150364438A1
公开(公告)日：2015-12-17
申请号：US14303465
申请日：2014-06-12
Applicant: QUALCOMM Incorporated
Inventor： Haiyong XU , Manoj Ashok KAKADE , Hua GUAN , Yue LI , Xiaoming CHEN , Ruey Kae ZANG
CPC classification number: H01L24/14 , H01L23/49816 , H01L23/49822 , H01L23/50 , H01L24/11 , H01L24/75 , H01L2224/1412 , H01L2924/15311 , H01L2924/301
Abstract: Methods and apparatuses for balancing current delivery. The method couples a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section. The method couples at least one ball of the BGA to the low resistance portion over a narrow trace.
Abstract translation: 用于平衡当前交付的方法和装置。 该方法通过形成三维截面的至少两个通孔将球栅阵列（BGA）的低电阻部分耦合到输入部分。 该方法将BGA中的至少一个球与窄电阻部分连接。
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10.发明公开公开(公告)号：US20240319755A1
公开(公告)日：2024-09-26
申请号：US18188891
申请日：2023-03-23
Applicant: QUALCOMM Incorporated
Inventor： Jize JIANG , Hua GUAN
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: Apparatus and methods for voltage regulation. One example circuit generally includes a first transistor having a source coupled to a Vin node and having a drain coupled to a Vout node; a second transistor having a drain coupled to a gate of the first transistor; a third transistor having a drain coupled to a source of the second transistor and having a source coupled to a reference potential node of the power supply circuit; a first amplifier having a first input coupled to a reference voltage node and having an output coupled to a gate of the third transistor, with feedback between the Vout node and a second input of the first amplifier; and a second amplifier having a first input coupled to a bias node, having a second input coupled to the source of the second transistor, and having an output coupled to a gate of the second transistor.
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