公开(公告)号：US20230417828A1

公开(公告)日：2023-12-28

申请号：US17808357

申请日：2022-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chengyue YU ,  Hua GUAN ,  Yingjie CHEN ,  Fan YANG ,  Yufei PAN ,  Jize JIANG ,  Shamim AHMED

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/2853 ,  G01R31/2891

Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

公开(公告)号：US20230198394A1

公开(公告)日：2023-06-22

申请号：US17554991

申请日：2021-12-17

Applicant: QUALCOMM Incorporated

Inventor： Jize JIANG ,  Hua GUAN

IPC: H02M3/158 ,  G05F1/445 ,  G05F1/573 ,  G05F1/575

CPC classification number: H02M3/158 ,  G05F1/445 ,  G05F1/573 ,  G05F1/575

Abstract: A power supply circuit and techniques for voltage regulation are described. Certain aspects provide a method of supplying power by a power supply circuit. The method generally includes: generating an output voltage based on a voltage at a Vin node via a first transistor having a gate coupled to a gate of a second transistor, wherein a source of the second transistor is coupled to the Vin node and wherein a drain of the second transistor is coupled a drain of a third transistor; and sourcing a current to the third transistor, wherein during a light load condition of the power supply circuit, the current varies based on the voltage at a Vout node of the power supply circuit, and during a heavy load condition of the power supply circuit, the current is limited based on a current threshold.

公开(公告)号：US20250020715A1

公开(公告)日：2025-01-16

申请号：US18420736

申请日：2024-01-23

Applicant: QUALCOMM Incorporated

Inventor： Chengyue YU ,  Hua GUAN ,  Yingjie CHEN ,  Fan YANG ,  Yufei PAN ,  Jize JIANG ,  Shamim AHMED

IPC: G01R31/28

Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

公开(公告)号：US20240319755A1

公开(公告)日：2024-09-26

申请号：US18188891

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Jize JIANG ,  Hua GUAN

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: Apparatus and methods for voltage regulation. One example circuit generally includes a first transistor having a source coupled to a Vin node and having a drain coupled to a Vout node; a second transistor having a drain coupled to a gate of the first transistor; a third transistor having a drain coupled to a source of the second transistor and having a source coupled to a reference potential node of the power supply circuit; a first amplifier having a first input coupled to a reference voltage node and having an output coupled to a gate of the third transistor, with feedback between the Vout node and a second input of the first amplifier; and a second amplifier having a first input coupled to a bias node, having a second input coupled to the source of the second transistor, and having an output coupled to a gate of the second transistor.

公开(公告)号：US20220206520A1

公开(公告)日：2022-06-30

申请号：US17138463

申请日：2020-12-30

Applicant: QUALCOMM Incorporated

Inventor： Jize JIANG ,  Hua GUAN ,  Kuan Chuang KOAY

IPC: G05F1/56

Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.

公开(公告)号：US20210336611A1

公开(公告)日：2021-10-28

申请号：US17247160

申请日：2020-12-02

Applicant: QUALCOMM Incorporated

Inventor： Jize JIANG ,  Kan LI

IPC: H03K5/04

Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

公开(公告)号：US20230280773A1

公开(公告)日：2023-09-07

申请号：US18315402

申请日：2023-05-10

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang KOAY ,  Hua GUAN ,  Jize JIANG

IPC: G05F1/56 ,  H03F3/16

CPC classification number: G05F1/56 ,  H03F3/16

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor.

公开(公告)号：US20220342434A1

公开(公告)日：2022-10-27

申请号：US17239377

申请日：2021-04-23

Applicant: QUALCOMM Incorporated

Inventor： Xiaodong MENG ,  Fan YANG ,  YuFei PAN ,  Hua GUAN ,  Kuan Chuang KOAY ,  Jize JIANG

IPC: G05F1/59 ,  G05F1/575 ,  H04B1/40

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

公开(公告)号：US20220308609A1

公开(公告)日：2022-09-29

申请号：US17213044

申请日：2021-03-25

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang KOAY ,  Hua GUAN ,  Jize JIANG

IPC: G05F1/56 ,  H03F3/16

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.