An integrated circuit device includes a semiconductor substrate having a memory area and a logic area. A memory cell in the memory area includes a select gate separated from a floating gate by a floating gate spacer. A select gate spacer is formed on a side of the select gate opposite the floating gate. The select gate spacer has a uniform thickness over most of the select gate. The first layer of the select gate spacer may be formed by oxidizing the select gate electrode. A second layer of the select gate spacer may be formed by atomic layer deposition. The memory area may be covered by a protective layer while spacers are formed adjacent logic gates in the logic region.