-
公开(公告)号:US20220320304A1
公开(公告)日:2022-10-06
申请号:US17845066
申请日:2022-06-21
发明人: Meng-Han Lin , Chih-Ren Hsieh
IPC分类号: H01L29/423 , H01L27/11521 , H01L27/11526 , H01L29/788 , H01L29/66 , H01L21/3213 , H01L21/02 , H01L21/28
摘要: An integrated circuit device includes a semiconductor substrate having a memory area and a logic area. A memory cell in the memory area includes a select gate separated from a floating gate by a floating gate spacer. A select gate spacer is formed on a side of the select gate opposite the floating gate. The select gate spacer has a uniform thickness over most of the select gate. The first layer of the select gate spacer may be formed by oxidizing the select gate electrode. A second layer of the select gate spacer may be formed by atomic layer deposition. The memory area may be covered by a protective layer while spacers are formed adjacent logic gates in the logic region.
-
公开(公告)号:US11864381B2
公开(公告)日:2024-01-02
申请号:US17567613
申请日:2022-01-03
发明人: Meng-Han Lin , Chih-Ren Hsieh , Ching-Wen Chan
摘要: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
-
公开(公告)号:US20240147718A1
公开(公告)日:2024-05-02
申请号:US18406592
申请日:2024-01-08
发明人: Meng-Han Lin , Chih-Ren Hsieh , Chen-Chin Liu , Chih-Pin Huang
IPC分类号: H10B41/50 , H01L21/033 , H01L21/28 , H01L21/308 , H01L21/321 , H01L29/423 , H01L29/51 , H10B41/10 , H10B41/41
CPC分类号: H10B41/50 , H01L21/0337 , H01L21/3086 , H01L21/3212 , H01L29/40117 , H01L29/42328 , H01L29/518 , H10B41/10 , H10B41/41 , H10B43/35
摘要: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.
-
-