Invention Application
- Patent Title: Heterogeneous Timing Closure For Clock-Skew Scheduling or Time Borrowing
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Application No.: US17856804Application Date: 2022-07-01
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Publication No.: US20220334609A1Publication Date: 2022-10-20
- Inventor: Ilya K. Ganusov , Grace Zgheib
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F1/10
- IPC: G06F1/10

Abstract:
Systems or methods for performing clock-skew scheduling or time borrowing using clock delays internal to hardened logic circuitry of an integrated circuit are provided. Such an integrated circuit may include programmable logic circuitry and hardened logic circuitry. The programmable logic circuitry may include at least a first path and a second path. The hardened logic circuitry may include input registers to receive the data from the first path and output registers to output the data to the second path. The hardened logic circuitry may also include first hardened logic circuitry to perform third operations between the input registers and the output registers. The hardened circuitry may also include a first delay circuit configurable to delay a clock signal by a first delay to the input registers or the output registers to enable time borrowing with the hardened logic circuitry.
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