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公开(公告)号:US20220334609A1
公开(公告)日:2022-10-20
申请号:US17856804
申请日:2022-07-01
Applicant: Intel Corporation
Inventor: Ilya K. Ganusov , Grace Zgheib
IPC: G06F1/10
Abstract: Systems or methods for performing clock-skew scheduling or time borrowing using clock delays internal to hardened logic circuitry of an integrated circuit are provided. Such an integrated circuit may include programmable logic circuitry and hardened logic circuitry. The programmable logic circuitry may include at least a first path and a second path. The hardened logic circuitry may include input registers to receive the data from the first path and output registers to output the data to the second path. The hardened logic circuitry may also include first hardened logic circuitry to perform third operations between the input registers and the output registers. The hardened circuitry may also include a first delay circuit configurable to delay a clock signal by a first delay to the input registers or the output registers to enable time borrowing with the hardened logic circuitry.
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公开(公告)号:US20210320661A1
公开(公告)日:2021-10-14
申请号:US17357869
申请日:2021-06-24
Applicant: Intel Corporation
Inventor: Scott Jeremy Weber , Ilya K. Ganusov
IPC: H03K19/17756 , H03K19/17736
Abstract: An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.
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公开(公告)号:US20220197855A1
公开(公告)日:2022-06-23
申请号:US17132663
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Ilya K. Ganusov , Ashish Gupta , Chee Hak Teh , Sean R. Atsatt , Scott Jeremy Weber , Parivallal Kannan , Aman Gupta , Gary Brian Wallichs
IPC: G06F15/78 , H04L12/933 , H04L12/773
Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
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公开(公告)号:US20220196735A1
公开(公告)日:2022-06-23
申请号:US17132683
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Sean R. Atsatt , Ilya K. Ganusov
IPC: G01R31/3177 , G01R31/317
Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
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公开(公告)号:US12197360B2
公开(公告)日:2025-01-14
申请号:US17359027
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Bee Yee Ng , Gaik Ming Chan , Ilya K. Ganusov
IPC: G06F13/28
Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).
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6.
公开(公告)号:US20240241650A1
公开(公告)日:2024-07-18
申请号:US18621940
申请日:2024-03-29
Applicant: Intel Corporation
Inventor: Sean R. Atsatt , Ilya K. Ganusov
CPC classification number: G06F3/0622 , G06F3/0655 , G06F3/0673 , G06N3/08
Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
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公开(公告)号:US11901896B2
公开(公告)日:2024-02-13
申请号:US17357869
申请日:2021-06-24
Applicant: Intel Corporation
Inventor: Scott Jeremy Weber , Ilya K. Ganusov
IPC: H03K19/17756 , H03K19/17736
CPC classification number: H03K19/17756 , H03K19/17736
Abstract: An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.
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8.
公开(公告)号:US20210011636A1
公开(公告)日:2021-01-14
申请号:US17033348
申请日:2020-09-25
Applicant: INTEL CORPORATION
Inventor: Sean R. Atsatt , Ilya K. Ganusov
Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
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公开(公告)号:US12248021B2
公开(公告)日:2025-03-11
申请号:US17132683
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Sean R. Atsatt , Ilya K. Ganusov
IPC: G01R31/3177 , G01R31/317 , G06F15/78 , H03K19/17758
Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
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公开(公告)号:US20250036591A1
公开(公告)日:2025-01-30
申请号:US18912321
申请日:2024-10-10
Applicant: Intel Corporation
Inventor: Ilya K. Ganusov , Ashish Gupta , Chee Hak Teh , Sean R. Atsatt , Scott Jeremy Weber , Parivallal Kannan , Aman Gupta , Gary Brian Wallichs
IPC: G06F15/78 , H04L45/60 , H04L49/109
Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
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