Invention Application
- Patent Title: DYNAMIC READ VOLTAGE TECHNIQUES
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Application No.: US17306562Application Date: 2021-05-03
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Publication No.: US20220351759A1Publication Date: 2022-11-03
- Inventor: Karthik Sarpatwari , Nevil N. Gajera , Jessica Chen , Lingming Yang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.
Public/Granted literature
- US11545194B2 Dynamic read voltage techniques Public/Granted day:2023-01-03
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