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    TESTING ACCESS FOR STACKED SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS
    1.
    发明申请
    TESTING ACCESS FOR STACKED SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20250087537A1

    公开(公告)日：2025-03-13

    申请号：US18789432

    申请日：2024-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Lingming Yang ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera

    IPC: H01L21/66 ,  H01L23/525 ,  H01L25/065 ,  H10B80/00

    Abstract: High-bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the HBM devices include a first die (e.g., an interface die), a plurality of second dies (e.g., memory dies) carried by the first die communicably coupled to the first die through a plurality of HBM bus through substrate vias (TSVs). The HBM devices also include an HBM testing component carried at least partially by an upper surface of an uppermost second die. The HBM testing component provides access to the first and second dies through an uppermost surface of the HBM device to test the HBM device during manufacturing. For example, the HBM testing component allows the first and second dies to be tested after the HBM device is mounted to a base substrate of a system-in-package without requiring any footprint for access pins on the base substrate.

    THERMAL DISSIPATION IN STACKED MEMORY DEVICES AND ASSOCIATED SYSTEMS AND METHODS
    2.
    发明申请
    THERMAL DISSIPATION IN STACKED MEMORY DEVICES AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20250031386A1

    公开(公告)日：2025-01-23

    申请号：US18777870

    申请日：2024-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Lingming Yang ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera

    IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

    Abstract: High-bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the HBM devices include a first die, a plurality of second dies carried by a signal routing region of the first die, and active through substrate vias (TSVs) positioned within a footprint of the signal routing region. The active TSVs extend from a first metallization layer in the first die to a second metallization layer in an uppermost memory die. The HBM devices also include a cooling network configured to transport heat away from the first die. For example, the cooling network can include a thermally conductive layer carried by a thermal region of the first die and cooling TSVs in contact with the thermally conductive layer. The thermally conductive TSVs extend from the thermally conductive layer to an elevation at or above a top surface of the uppermost memory die.

    Dynamic read voltage techniques
    4.
    发明授权
    Dynamic read voltage techniques 有权

    公开(公告)号：US11545194B2

    公开(公告)日：2023-01-03

    申请号：US17306562

    申请日：2021-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Jessica Chen ,  Lingming Yang

    IPC: G11C7/10

    Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

    Programming Intermediate State to Store Data in Self-Selecting Memory Cells
    5.
    发明申请
    Programming Intermediate State to Store Data in Self-Selecting Memory Cells 有权

    公开(公告)号：US20220392535A1

    公开(公告)日：2022-12-08

    申请号：US17336913

    申请日：2021-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  Yen Chun Lee ,  Jessica Chen ,  Francesco Douglas Verna-Ketel

    IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08

    Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.

    Restoring memory cell threshold voltages
    6.
    发明授权
    Restoring memory cell threshold voltages 有权

    公开(公告)号：US10964385B1

    公开(公告)日：2021-03-30

    申请号：US16684526

    申请日：2019-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Lingming Yang ,  Nevil Gajera ,  Karthik Sarpatwari

    IPC: G11C7/00 ,  G11C13/00

    Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

    Data correction scheme with reduced device overhead
    7.
    发明授权
    Data correction scheme with reduced device overhead 有权

    公开(公告)号：US12210413B2

    公开(公告)日：2025-01-28

    申请号：US18211881

    申请日：2023-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Joseph M. McCrate ,  Marco Sforzin ,  Paolo Amato ,  Lingming Yang ,  Nevil N. Gajera

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

    Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.

    Method and memory system for writing data to dram submodules based on the data traffic demand
    9.
    发明授权
    Method and memory system for writing data to dram submodules based on the data traffic demand 有权

    公开(公告)号：US12013756B2

    公开(公告)日：2024-06-18

    申请号：US17894893

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Lingming Yang ,  Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Nevil Gajera

    IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0689 ,  G06F11/1096

    Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.

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