A memory device includes a cell region including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines disposed therein, where each of the plurality of memory cells includes a switch element and a memory element connected to each other in series between a corresponding word line and a corresponding bit line, and a peripheral circuit region including a control logic configured to, when a read command for a selected memory cell among the memory cells is received from an external controller, input a pre-voltage to the selected memory cell before reading data of the selected memory cell. The control logic is configured to determine a level of the pre-voltage with reference to an elapsed time after programming of the selected memory cell.