Invention Application
- Patent Title: Transistor Gate Profile Optimization
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Application No.: US17874295Application Date: 2022-07-27
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Publication No.: US20220359511A1Publication Date: 2022-11-10
- Inventor: Chi-Sheng Lai , Wei-Chung Sun , Li-Ting Chen , Kuei-Yu Kao , Chih-Han Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/78 ; H01L21/8234 ; H01L29/66

Abstract:
A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
Information query
IPC分类: