中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.014 seconds)

    Transistor Gate Profile Optimization
    1.
    发明申请
    Transistor Gate Profile Optimization 有权

    公开(公告)号：US20240379672A1

    公开(公告)日：2024-11-14

    申请号：US18780798

    申请日：2024-07-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

    Gate Formation Process
    3.
    发明申请
    Gate Formation Process 有权

    公开(公告)号：US20210265219A1

    公开(公告)日：2021-08-26

    申请号：US16800871

    申请日：2020-02-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/308

    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

    Transistor Gate Profile Optimization
    5.
    发明申请
    Transistor Gate Profile Optimization 有权

    公开(公告)号：US20220359511A1

    公开(公告)日：2022-11-10

    申请号：US17874295

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

    Alignment Structure for Semiconductor Device and Method of Forming Same
    6.
    发明申请
    Alignment Structure for Semiconductor Device and Method of Forming Same 有权

    公开(公告)号：US20240387397A1

    公开(公告)日：2024-11-21

    申请号：US18786474

    申请日：2024-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L23/544 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

    GATE FORMATION PROCESS
    7.
    发明申请
    GATE FORMATION PROCESS 有权

    公开(公告)号：US20220181215A1

    公开(公告)日：2022-06-09

    申请号：US17682621

    申请日：2022-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/308

    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

    Transistor Gate Profile Optimization
    8.
    发明申请
    Transistor Gate Profile Optimization 有权

    公开(公告)号：US20210257359A1

    公开(公告)日：2021-08-19

    申请号：US16899268

    申请日：2020-06-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

Patent Agency Ranking