Invention Publication
- Patent Title: NON-VOLATILE MEMORY WITH STAGGERED RAMP DOWN AT THE END OF PRE-CHARGING
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Application No.: US17527747Application Date: 2021-11-16
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Publication No.: US20230154538A1Publication Date: 2023-05-18
- Inventor: Xiang Yang , Fanqi Wu , Jiacen Guo , Jiahui Yuan
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/04 ; G11C16/08 ; H01L27/11582 ; G11C16/24 ; G11C16/34

Abstract:
In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.
Public/Granted literature
- US11862249B2 Non-volatile memory with staggered ramp down at the end of pre-charging Public/Granted day:2024-01-02
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