Invention Publication
- Patent Title: PIN DIODE INCLUDING A CONDUCTIVE LAYER, AND FABRICATION PROCESS
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Application No.: US18096791Application Date: 2023-01-13
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Publication No.: US20230154975A1Publication Date: 2023-05-18
- Inventor: Pascal FORNARA
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Priority: FR 00384 2019.01.16 FR 00385 2019.01.16
- The original application number of the division: US17370397 2021.07.08
- Main IPC: H01L29/04
- IPC: H01L29/04 ; H01L29/66 ; H01L29/861 ; H01L29/868

Abstract:
A PIN diode includes a first polycrystalline silicon region doped with a P-type of conductivity, a second polycrystalline silicon region doped with an N-type of conductivity and an intrinsic polycrystalline silicon region. At least the intrinsic polycrystalline silicon region is configured to include fluorine atoms. A polycrystalline silicon bar may include the first polycrystalline silicon region, the second polycrystalline silicon region and the intrinsic polycrystalline silicon region. The polycrystalline silicon bar may be supported by an insulating region within a semiconductor substrate.
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