公开(公告)号：US20230326885A1

公开(公告)日：2023-10-12

申请号：US18210392

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: H01L23/62 ,  H01H85/02 ,  H01L23/525 ,  H01L21/66

CPC classification number: H01L23/62 ,  H01H85/0241 ,  H01L23/5256 ,  H01L22/34 ,  H01H2085/0283

Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

公开(公告)号：US20230317637A1

公开(公告)日：2023-10-05

申请号：US18206923

申请日：2023-06-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00 ,  H01L29/788 ,  G06F21/75 ,  G06F21/79 ,  H01L23/522 ,  H10B41/35

CPC classification number: H01L23/573 ,  H01L29/7883 ,  H01L23/576 ,  G06F21/75 ,  G06F21/79 ,  H01L23/5223 ,  H10B41/35 ,  G06F21/87

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US20230223448A1

公开(公告)日：2023-07-13

申请号：US18094023

申请日：2023-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Christian RIVERO ,  Franck JULIEN

IPC: H01L29/40 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/401 ,  H01L29/456 ,  H01L21/76843 ,  H01L21/76858 ,  H01L23/53266 ,  H01L23/5226

Abstract: A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.

公开(公告)号：US20220120589A1

公开(公告)日：2022-04-21

申请号：US17504021

申请日：2021-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: G01D5/24 ,  H01L27/06 ,  H01L29/786 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.

公开(公告)号：US20210091015A1

公开(公告)日：2021-03-25

申请号：US17113645

申请日：2020-12-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00

Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.

公开(公告)号：US20230326883A1

公开(公告)日：2023-10-12

申请号：US18210286

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

IPC: H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01 ,  H01L27/10

CPC classification number: H01L23/573 ,  G04F1/005 ,  H01L21/705 ,  H01L27/013 ,  H01L27/101

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US20230154975A1

公开(公告)日：2023-05-18

申请号：US18096791

申请日：2023-01-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

CPC classification number: H01L29/04 ,  H01L29/6609 ,  H01L29/8615 ,  H01L29/868

Abstract: A PIN diode includes a first polycrystalline silicon region doped with a P-type of conductivity, a second polycrystalline silicon region doped with an N-type of conductivity and an intrinsic polycrystalline silicon region. At least the intrinsic polycrystalline silicon region is configured to include fluorine atoms. A polycrystalline silicon bar may include the first polycrystalline silicon region, the second polycrystalline silicon region and the intrinsic polycrystalline silicon region. The polycrystalline silicon bar may be supported by an insulating region within a semiconductor substrate.

公开(公告)号：US20210126000A1

公开(公告)日：2021-04-29

申请号：US17141498

申请日：2021-01-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

公开(公告)号：US20200227517A1

公开(公告)日：2020-07-16

申请号：US16739753

申请日：2020-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

公开(公告)号：US20200043936A1

公开(公告)日：2020-02-06

申请号：US16525780

申请日：2019-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

IPC: H01L27/112 ,  H01L23/00 ,  H01L23/525 ,  G11C17/16 ,  G11C17/18

Abstract: An integrated circuit includes at least one antifuse element. The antifuse element is formed from a semiconductor substrate, a trench extending down from a first face of the semiconductor substrate into the semiconductor substrate, a first conductive layer housed in the trench and extending down from the first face of the semiconductor substrate into the semiconductor substrate, a dielectric layer on the first face of the semiconductor substrate, and a second conductive layer on the dielectric layer. A program transistor selectively electrically couples the second conductive layer to a program voltage in response to a program signal. A program/read transistor selectively electrically couples the first conductive layer to a ground voltage in response to the program signal and in response to a read signal. A read transistor selectively electrically couples the second conductive layer to a read amplifier in response to the read signal.