Control logic in a memory device causes a program voltage to be applied to a selected data wordline of a plurality of wordlines of a block of a memory array for a pulse duration period during a programming operation. The control logic further causes a first pass voltage to be applied to one or more unselected data wordlines of the plurality of wordlines of the block for the pulse duration period and causes a second pass voltage to be applied to a last unselected data wordline of the plurality of wordlines of the block for at least a first portion of the pulse duration period, wherein the second pass voltage has a lower magnitude than the first pass voltage.