Invention Publication
- Patent Title: Hierarchical ROM Encoder System For Performing Address Fault Detection In A Memory System
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Application No.: US17669793Application Date: 2022-02-11
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Publication No.: US20230170035A1Publication Date: 2023-06-01
- Inventor: Xiaozhou Qian , YAOHUA ZHU
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Priority: CN 2111444122.6 2021.11.30
- Main IPC: G11C29/04
- IPC: G11C29/04 ; G11C8/10
Abstract:
Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.
Public/Granted literature
- US11798644B2 Hierarchical ROM encoder system for performing address fault detection in a memory system Public/Granted day:2023-10-24
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