公开(公告)号：US20230170035A1

公开(公告)日：2023-06-01

申请号：US17669793

申请日：2022-02-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  YAOHUA ZHU

IPC: G11C29/04 ,  G11C8/10

CPC classification number: G11C29/04 ,  G11C8/10

Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.