A semiconductor package includes a first semiconductor chip including first pads and a first insulating layer, and a second semiconductor chip including second upper pads, a second insulating layer, second lower pads, and through electrodes connecting the second upper pads and the second lower pads to each other. The package includes a third semiconductor chip including third upper pads, an upper barrier layer, a third insulating layer, third lower pads, a lower barrier layer, and dummy electrode structures connecting the third upper pads and the third lower pads to each other. The package includes an encapsulant below the first semiconductor chip to seal at least a portion of each of the second and third semiconductor chips and cover side surfaces of the third lower pads. The package includes bump structures below the encapsulant and the second and third semiconductor chips.