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公开(公告)号:US20240030083A1
公开(公告)日:2024-01-25
申请号:US18187444
申请日:2023-03-21
发明人: Yikoan HONG , Seokho KIM , Kwangjin MOON
IPC分类号: H01L23/34 , H01L25/065 , H01L23/00
CPC分类号: H01L23/34 , H01L25/0657 , H01L24/08 , H01L2224/08146 , H01L2224/08221 , H01L2924/182
摘要: A semiconductor package includes a semiconductor substrate and a semiconductor chip in contact with the semiconductor substrate. The semiconductor chip has a first surface facing the semiconductor substrate and an opposite second surface. The semiconductor chip has a die region, an edge region extending around the die region and a plurality of air exhaust passages extending from the die region to an outer surface of the edge region in the first surface of the semiconductor chip. Each of the air exhaust passages includes an inlet having a first passage area, and an outlet having a second passage area greater than the first passage area.
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公开(公告)号:US20220037235A1
公开(公告)日:2022-02-03
申请号:US17185166
申请日:2021-02-25
发明人: Hakseung LEE , Kwangjin MOON , Hyungjun JEON , Hyoukyung CHO
IPC分类号: H01L23/48 , H01L23/522 , H01L23/528 , H01L23/00
摘要: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.
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公开(公告)号:US20220406740A1
公开(公告)日:2022-12-22
申请号:US17544081
申请日:2021-12-07
发明人: Taeyeong KIM , Taeseong KIM , Kwangjin MOON , Hyungjun JEON
IPC分类号: H01L23/00 , H01L27/146 , H01L23/488
摘要: A semiconductor device including a first structure including a first dielectric layer and a first conductive pattern in the first dielectric layer, the first conductive pattern including a first conductive material and a first bonding enhancement material; a second structure including a second dielectric layer and a second conductive pattern in the second dielectric layer, the second dielectric layer directly contacting the first dielectric layer, the second conductive pattern directly contacting the first conductive pattern; and a first bonding enhancement layer between the first conductive pattern and the second dielectric layer, wherein the first bonding enhancement layer includes the first bonding enhancement material or a material of the second dielectric layer, and the first bonding enhancement material includes a material having a higher bonding force to the material of the second dielectric layer than a bonding force of the first conductive material to the material of the second dielectric layer.
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公开(公告)号:US20220367321A1
公开(公告)日:2022-11-17
申请号:US17713421
申请日:2022-04-05
发明人: Hyungjun JEON , Kwangjin MOON , Myungjoo PARK , Hakseung LEE , Sonkwan HWANG
IPC分类号: H01L23/48 , H01L23/528 , H01L23/522 , H01L23/00
摘要: A semiconductor device includes front and back side structures on first and second surfaces of a substrate, respectively, and first and second through electrodes penetrating the substrate. The front side structure includes a circuit device, a first front side conductive pattern at a first level, a second front side conductive pattern at a second level, a lower insulating structure, and first to third insulating structures. The back side structure includes a first and a second back side conductive pattern on the same level. The first through electrode contacts the first back side conductive pattern and the first front side conductive pattern. The second through electrode contacts the second back side conductive pattern and the second front side conductive pattern. The first front side conductive pattern penetrates the second insulating structure and at least a portion of the third insulating structure.
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公开(公告)号:US20220310485A1
公开(公告)日:2022-09-29
申请号:US17514218
申请日:2021-10-29
发明人: Sonkwan HWANG , Taeseong KIM , Hoonjoo NA , Kwangjin MOON , Hyungjun JEON
IPC分类号: H01L23/48 , H01L23/528 , H01L27/088 , H01L25/065 , H01L21/768
摘要: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.
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公开(公告)号:US20240274509A1
公开(公告)日:2024-08-15
申请号:US18610651
申请日:2024-03-20
发明人: Hyoukyung CHO , Hojin LEE , Kwangjin MOON
IPC分类号: H01L23/48 , H01L21/762 , H01L21/768 , H01L25/065 , H01L29/06
CPC分类号: H01L23/481 , H01L21/76224 , H01L21/76816 , H01L21/76898 , H01L25/0657 , H01L29/0649 , H01L2225/06544
摘要: A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.
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公开(公告)号:US20240234377A9
公开(公告)日:2024-07-11
申请号:US18536332
申请日:2023-12-12
发明人: Jinnam KIM , Seokho KIM , Hoonjoo NA , Kwangjin MOON
IPC分类号: H01L25/065 , H01L23/00 , H01L23/48 , H01L25/18
CPC分类号: H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/48 , H01L25/18 , H01L2224/05147 , H01L2224/08145 , H01L2224/16227 , H01L2224/48227 , H01L2225/06541
摘要: A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.
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公开(公告)号:US20240136334A1
公开(公告)日:2024-04-25
申请号:US18536332
申请日:2023-12-12
发明人: Jinnam KIM , Seokho KIM , Hoonjoo NA , Kwangjin MOON
IPC分类号: H01L25/065 , H01L23/00 , H01L23/48 , H01L25/18
CPC分类号: H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/48 , H01L25/18 , H01L2224/05147 , H01L2224/08145 , H01L2224/16227 , H01L2224/48227 , H01L2225/06541
摘要: A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.
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公开(公告)号:US20240047305A1
公开(公告)日:2024-02-08
申请号:US18199541
申请日:2023-05-19
发明人: Seungha OH , Jaewon HWANG , Kwangjin MOON , Hojin LEE , Hyungjun JEON
IPC分类号: H01L23/48 , H01L23/528 , H01L27/088 , H01L21/768 , H01L23/00
CPC分类号: H01L23/481 , H01L23/5286 , H01L27/0886 , H01L27/088 , H01L21/76898 , H01L24/13 , H01L2224/13007 , H01L2224/1411 , H01L24/14
摘要: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface; a power via penetrating between the first surface and the second surface of the substrate; a cell part including a plurality of individual elements having different thicknesses inside the substrate, and a recess positioned between the individual elements; a signal wiring part on the first surface of the substrate and including an upper multilayer wiring layer connected to the power via; a power transmission network part under the second surface of the substrate and including a lower multilayer wiring layer connected to the power via; and an external connection terminal under the power transmission network part and connected to the lower multilayer wiring layer, wherein the substrate includes a plurality of regions having different thicknesses.
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公开(公告)号:US20180053797A1
公开(公告)日:2018-02-22
申请号:US15630063
申请日:2017-06-22
发明人: Ho-Jin LEE , Kwangjin MOON , Seokho KIM , Sukchul BANG , Jin Ho AN , Naein LEE
IPC分类号: H01L27/146
CPC分类号: H01L27/1463 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14645 , H01L27/14683 , H01L2224/11
摘要: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.
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