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公开(公告)号:US20220223555A1
公开(公告)日:2022-07-14
申请号:US17709856
申请日:2022-03-31
发明人: Hyungjun JEON , Kwangjin MOON , Hakseung LEE , Hyoukyung CHO
IPC分类号: H01L23/00 , H01L25/065 , H01L21/683 , H01L21/78 , H01L25/00
摘要: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.
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公开(公告)号:US20240047305A1
公开(公告)日:2024-02-08
申请号:US18199541
申请日:2023-05-19
发明人: Seungha OH , Jaewon HWANG , Kwangjin MOON , Hojin LEE , Hyungjun JEON
IPC分类号: H01L23/48 , H01L23/528 , H01L27/088 , H01L21/768 , H01L23/00
CPC分类号: H01L23/481 , H01L23/5286 , H01L27/0886 , H01L27/088 , H01L21/76898 , H01L24/13 , H01L2224/13007 , H01L2224/1411 , H01L24/14
摘要: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface; a power via penetrating between the first surface and the second surface of the substrate; a cell part including a plurality of individual elements having different thicknesses inside the substrate, and a recess positioned between the individual elements; a signal wiring part on the first surface of the substrate and including an upper multilayer wiring layer connected to the power via; a power transmission network part under the second surface of the substrate and including a lower multilayer wiring layer connected to the power via; and an external connection terminal under the power transmission network part and connected to the lower multilayer wiring layer, wherein the substrate includes a plurality of regions having different thicknesses.
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公开(公告)号:US20220037235A1
公开(公告)日:2022-02-03
申请号:US17185166
申请日:2021-02-25
发明人: Hakseung LEE , Kwangjin MOON , Hyungjun JEON , Hyoukyung CHO
IPC分类号: H01L23/48 , H01L23/522 , H01L23/528 , H01L23/00
摘要: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.
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公开(公告)号:US20220406740A1
公开(公告)日:2022-12-22
申请号:US17544081
申请日:2021-12-07
发明人: Taeyeong KIM , Taeseong KIM , Kwangjin MOON , Hyungjun JEON
IPC分类号: H01L23/00 , H01L27/146 , H01L23/488
摘要: A semiconductor device including a first structure including a first dielectric layer and a first conductive pattern in the first dielectric layer, the first conductive pattern including a first conductive material and a first bonding enhancement material; a second structure including a second dielectric layer and a second conductive pattern in the second dielectric layer, the second dielectric layer directly contacting the first dielectric layer, the second conductive pattern directly contacting the first conductive pattern; and a first bonding enhancement layer between the first conductive pattern and the second dielectric layer, wherein the first bonding enhancement layer includes the first bonding enhancement material or a material of the second dielectric layer, and the first bonding enhancement material includes a material having a higher bonding force to the material of the second dielectric layer than a bonding force of the first conductive material to the material of the second dielectric layer.
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公开(公告)号:US20220367321A1
公开(公告)日:2022-11-17
申请号:US17713421
申请日:2022-04-05
发明人: Hyungjun JEON , Kwangjin MOON , Myungjoo PARK , Hakseung LEE , Sonkwan HWANG
IPC分类号: H01L23/48 , H01L23/528 , H01L23/522 , H01L23/00
摘要: A semiconductor device includes front and back side structures on first and second surfaces of a substrate, respectively, and first and second through electrodes penetrating the substrate. The front side structure includes a circuit device, a first front side conductive pattern at a first level, a second front side conductive pattern at a second level, a lower insulating structure, and first to third insulating structures. The back side structure includes a first and a second back side conductive pattern on the same level. The first through electrode contacts the first back side conductive pattern and the first front side conductive pattern. The second through electrode contacts the second back side conductive pattern and the second front side conductive pattern. The first front side conductive pattern penetrates the second insulating structure and at least a portion of the third insulating structure.
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公开(公告)号:US20220310485A1
公开(公告)日:2022-09-29
申请号:US17514218
申请日:2021-10-29
发明人: Sonkwan HWANG , Taeseong KIM , Hoonjoo NA , Kwangjin MOON , Hyungjun JEON
IPC分类号: H01L23/48 , H01L23/528 , H01L27/088 , H01L25/065 , H01L21/768
摘要: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.
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公开(公告)号:US20230361004A1
公开(公告)日:2023-11-09
申请号:US18354068
申请日:2023-07-18
发明人: Sonkwan HWANG , Taeseong KIM , Hoonjoo NA , Kwangjin MOON , Hyungjun JEON
IPC分类号: H01L23/48 , H01L27/088 , H01L25/065 , H01L21/768 , H01L23/528
CPC分类号: H01L23/481 , H01L27/0886 , H01L25/0657 , H01L21/76898 , H01L23/528 , H01L2224/0603 , H01L2225/06513 , H01L2225/06544 , H01L24/06
摘要: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.
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公开(公告)号:US20230178533A1
公开(公告)日:2023-06-08
申请号:US17891629
申请日:2022-08-19
发明人: Hyungjun JEON , Kwangjin MOON
CPC分类号: H01L25/18 , H01L24/08 , H01L23/3157 , H01L24/05 , H01L23/481 , H01L24/80 , H01L2224/08145 , H01L2224/05647 , H01L2224/05655 , H01L2224/05644 , H01L2224/05639 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/80379
摘要: A semiconductor package includes a first semiconductor chip including first pads and a first insulating layer, and a second semiconductor chip including second upper pads, a second insulating layer, second lower pads, and through electrodes connecting the second upper pads and the second lower pads to each other. The package includes a third semiconductor chip including third upper pads, an upper barrier layer, a third insulating layer, third lower pads, a lower barrier layer, and dummy electrode structures connecting the third upper pads and the third lower pads to each other. The package includes an encapsulant below the first semiconductor chip to seal at least a portion of each of the second and third semiconductor chips and cover side surfaces of the third lower pads. The package includes bump structures below the encapsulant and the second and third semiconductor chips.
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公开(公告)号:US20210305186A1
公开(公告)日:2021-09-30
申请号:US17035215
申请日:2020-09-28
发明人: Hyungjun JEON , Kwangjin MOON , Hakseung LEE , Hyoukyung CHO
IPC分类号: H01L23/00 , H01L25/065 , H01L21/683 , H01L21/78 , H01L25/00
摘要: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.
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