The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.