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公开(公告)号：US20230195679A1
公开(公告)日：2023-06-22
申请号：US18063436
申请日：2022-12-08
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.
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公开(公告)号：US20230195680A1
公开(公告)日：2023-06-22
申请号：US18063453
申请日：2022-12-08
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.
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