Invention Publication
- Patent Title: SOLDER INTERCONNECT HIERARCHY FOR HETEROGENEOUS ELECTRONIC DEVICE PACKAGING
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Application No.: US17558297Application Date: 2021-12-21
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Publication No.: US20230197660A1Publication Date: 2023-06-22
- Inventor: Yue DENG , Jung Kyu HAN , Liang HE , Gang DUAN , Rahul N. MANEPALLI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498

Abstract:
A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.
Information query
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