公开(公告)号：US20230086920A1

公开(公告)日：2023-03-23

申请号：US17481245

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Liang HE ,  Jisu JIANG ,  Jung Kyu HAN ,  Gang DUAN ,  Yosuke KANAOKA ,  Jason M. GAMBA ,  Bai NIE ,  Robert Alan MAY ,  Kimberly A. DEVINE ,  Mitchell ARMSTRONG ,  Yue DENG

IPC: H01L23/31 ,  H01L23/22

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a dam structure on a substrate that is proximate to a die coupled with the substrate, where the dam decreases the risk of die shift during encapsulation material flow over the die during the manufacturing process. The dam structure may fully encircle the die. During encapsulation material flow, the dam structure creates a cavity that moderates the different flow rates of material that otherwise would exert different pressures the sides of the die and cause to die to shift its position on the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213164A1

公开(公告)日：2024-06-27

申请号：US18089483

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Gang DUAN ,  Liang HE ,  Ziyin LIN ,  Elizabeth NOFEN ,  Yiqun BAI ,  Jonathan ATKINS ,  Jesus S. NIETO PESCADOR ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5381 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/14 ,  H01L2224/16104

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. In an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. In an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. In an embodiment, a non-conductive film (NCF) is around the solder between the first pads and the second pads.

公开(公告)号：US20240186263A1

公开(公告)日：2024-06-06

申请号：US18060574

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Hong Seung YEON ,  Liang HE ,  Whitney BRYKS ,  Jung Kyu HAN ,  Gang DUAN

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L2224/32225 ,  H01L2924/3511

Abstract: The present disclosure is directed to a semiconductor carrier platform having a support panel with a top surface and a bottom surface, with the top surface providing a working surface for assembling IC packages using panel-level packaging technology. In an aspect, a backside molding layer may be positioned on the bottom surface of the support panel to prevent or correct any panel warpage. In another aspect, a removable film may be positioned between the bottom surface of the support panel and the backside molding layer to allow the support panel to be readily cleaned and reused.

公开(公告)号：US20230197660A1

公开(公告)日：2023-06-22

申请号：US17558297

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yue DENG ,  Jung Kyu HAN ,  Liang HE ,  Gang DUAN ,  Rahul N. MANEPALLI

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2924/014

Abstract: A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.

公开(公告)号：US20230091379A1

公开(公告)日：2023-03-23

申请号：US17482275

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Liang HE ,  Yeasir ARAFAT ,  Jung Kyu HAN ,  Ali LEHAF ,  Gang DUAN ,  Steve S. CHO ,  Yue DENG

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/528

Abstract: Embodiments disclosed herein include electronic packages with first level interconnects that comprise a first layer. In an embodiment, the electronic package comprises a package substrate and a pad on the package substrate. In an embodiment, the pad comprises copper. In an embodiment, a first layer is over the pad. In an embodiment, the first layer comprises iron. In an embodiment, a solder is over the first layer, and a die is coupled to the package substrate by the solder.