Invention Publication
- Patent Title: PACKAGING ARCHITECTURE WITH INTEGRATED CIRCUIT DIES OVER INPUT/OUTPUT INTERFACES
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Application No.: US17552845Application Date: 2021-12-16
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Publication No.: US20230197675A1Publication Date: 2023-06-22
- Inventor: Gerald S. Pasdast , Yidnekachew Mekonnen , Adel A. Elsherbini , Peipei Wang , Vivek Kumar Rajan , Georgios Dogiamis
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/48 ; H01L23/00

Abstract:
Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die, the first IC die comprising an input/output (IO) circuit; and a plurality of IC dies, the plurality of IC dies comprising a second IC die, the second IC die comprising a microcontroller circuit to control the IO circuit, wherein the first IC die and the plurality of IC dies are coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.
Information query
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