Invention Publication
- Patent Title: PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY
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Application No.: US17557622Application Date: 2021-12-21
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Publication No.: US20230197677A1Publication Date: 2023-06-22
- Inventor: Adel A. Elsherbini , Stephen R. Van Doren , Ritu Gupta , Gerald S. Pasdast , Robert J. Munoz , Shawna M. Liff
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L25/065
- IPC: H01L25/065

Abstract:
A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.
Information query
IPC分类: