Invention Publication
- Patent Title: Negative Capacitance Transistor With A Diffusion Blocking Layer
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Application No.: US18168417Application Date: 2023-02-13
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Publication No.: US20230197851A1Publication Date: 2023-06-22
- Inventor: Chi-Hsing Hsu , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang , Sai-Hooi Yeong
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L27/088 ; H01L29/06

Abstract:
A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.
Public/Granted literature
- US12272751B2 Negative capacitance transistor with a diffusion blocking layer Public/Granted day:2025-04-08
Information query
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