Invention Publication
- Patent Title: METAL CHALCOGENIDE TRANSISTORS WITH DEFECTED CHANNEL TRANSITION LAYER
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Application No.: US17560069Application Date: 2021-12-22
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Publication No.: US20230197860A1Publication Date: 2023-06-22
- Inventor: Carl H. Naylor , Kirby Maxey , Chelsey Dorow , Sudarat Lee , Kevin O'Brien , Ashish V. Penumatcha , Scott B. Clendenning , Uygar Avci , Matthew Metz
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/66

Abstract:
A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.
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