- 专利标题: VIA-FIRST PROCESS FOR CONNECTING A CONTACT AND A GATE ELECTRODE
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申请号: US18302156申请日: 2023-04-18
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公开(公告)号: US20230253244A1公开(公告)日: 2023-08-10
- 发明人: Chao-Hsun Wang , Mei-Yun Wang , Kuo-Yi Chao , Wang-Jung Hsueh
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 分案原申请号: US16797375 2020.02.21
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L21/311 ; H01L23/528 ; H01L21/02 ; H01L23/532 ; H10B10/00
摘要:
Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
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