公开(公告)号：US20220223517A1

公开(公告)日：2022-07-14

申请号：US17144724

申请日：2021-01-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Wang-Jung Hsueh ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Sheng-Hsiung Wang ,  Shih-Hsien Huang

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/321 ,  H01L29/40

摘要： A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

公开(公告)号：US20230260900A1

公开(公告)日：2023-08-17

申请号：US18309460

申请日：2023-04-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Wang-Jung Hsueh ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Sheng-Hsiung Wang ,  Shih-Hsien Huang

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L29/40 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L23/53257 ,  H01L29/401 ,  H01L21/76802 ,  H01L21/32115 ,  H01L23/5283

摘要： A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

公开(公告)号：US11670544B2

公开(公告)日：2023-06-06

申请号：US17533434

申请日：2021-11-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Mei-Yun Wang ,  Kuo-Yi Chao ,  Wang-Jung Hsueh

IPC分类号： H01L21/768 ,  H01L27/11 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

CPC分类号： H01L21/76816 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/1104

摘要： Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

公开(公告)号：US20220093456A1

公开(公告)日：2022-03-24

申请号：US17533434

申请日：2021-11-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Mei-Yun Wang ,  Kuo-Yi Chao ,  Wang-Jung Hsueh

IPC分类号： H01L21/768 ,  H01L27/11 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

摘要： Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

公开(公告)号：US12125743B2

公开(公告)日：2024-10-22

申请号：US18302156

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Mei-Yun Wang ,  Kuo-Yi Chao ,  Wang-Jung Hsueh

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B10/00

CPC分类号： H01L21/76816 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H10B10/12

摘要： Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

公开(公告)号：US11915971B2

公开(公告)日：2024-02-27

申请号：US17661734

申请日：2022-05-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Wang-Jung Hsueh ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L21/76807 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/76877 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/4232 ,  H01L29/4966 ,  H01L21/823475

摘要： A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

公开(公告)号：US20230253244A1

公开(公告)日：2023-08-10

申请号：US18302156

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Mei-Yun Wang ,  Kuo-Yi Chao ,  Wang-Jung Hsueh

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532 ,  H10B10/00

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L21/31116 ,  H01L23/5283 ,  H01L21/76834 ,  H01L21/02063 ,  H01L23/53266 ,  H10B10/12

摘要： Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

公开(公告)号：US20230033570A1

公开(公告)日：2023-02-02

申请号：US17444132

申请日：2021-07-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Chieh WU ,  Pang-Chi Wu ,  Wang-Jung Hsueh ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Yi-Chun Chang ,  Yuan-Tien Tu

IPC分类号： H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

摘要： A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

公开(公告)号：US11640936B2

公开(公告)日：2023-05-02

申请号：US17144724

申请日：2021-01-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Wang-Jung Hsueh ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Sheng-Hsiung Wang ,  Shih-Hsien Huang

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L29/40 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528

摘要： A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.