- 专利标题: SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE
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申请号: US17679178申请日: 2022-02-24
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公开(公告)号: US20230267259A1公开(公告)日: 2023-08-24
- 发明人: Navneet Jain , Mahbub Rashed
- 申请人: GlobalFoundries U.S. Inc.
- 申请人地址: US NY Malta
- 专利权人: GlobalFoundries U.S. Inc.
- 当前专利权人: GlobalFoundries U.S. Inc.
- 当前专利权人地址: US NY Malta
- 主分类号: G06F30/392
- IPC分类号: G06F30/392 ; G06F30/398
摘要:
Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.
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